1. Field of Invention
The present invention relates to a display, and particularly to a level shift circuit of the source driver in the display.
2. Description of Related Art
Level shift circuits are utilized in integrated circuits for shifting the voltage levels of the input signals to provide the output signals having the higher output voltage levels.
FIG. 1 is a circuit diagram depicting a level shift circuit 100 of the prior art. The level shift circuit 100 has a first P-type transistor 110, a second P-type transistor 120, a first N-type transistor 130, and a second N-type transistor 140. The level shift circuit 100 receives complementary input signals from input terminals IN1 and IN2 and converts the input signals into output signals for outputting to output terminals OUT1 and OUT2.
The first P-type transistor 110 has a source connected to a power source VDDA, a gate connected to the first output terminal IN1, a drain connected to the second output terminal OUT2. The second P-type transistor 120 has a source connected to the power source VDDA, a gate connected to the second output terminal OUT2, a drain connected to the first output terminal OUT1.
The first N-type transistor 130 has a source connected to a second supply voltage VSSA, a gate connected to a first input terminal IN1, a drain connected to the second output terminal OUT2. The second N-type transistor 140 has a source connected to the second supply voltage VSSA, a gate connected to a second input terminal IN2, a drain connected to the first output terminal OUT1.
Due to the gate of the first P-type transistor 110 is connected to the drain of the second N-type transistor 140, and the gate of the second P-type transistor 120 is connected to the drain of the first N-type transistor 130, therefore, if the first input signal IN1 is high and the second input signal IN2 is low, then the first N-type transistor 130 is turned on and the second N-type transistor 140 is turned off, which results in OUT1 coupling to the VDDA and OUT2 coupling to the VSSA. If the first input signal IN1 is low and the second input signal IN2 is high, then the first N-type transistor 130 is turned off and the second N-type transistor 140 is turned on, which results in OUT1 coupling to the VSSA and OUT2 coupling to the VDDA.
However, the above-mentioned conventional level shift circuit 100 has a drawback of a longer transitional time when the input voltage (for example, IN1 or IN2) is too small. For example, when the first input terminal IN1 of the first N-type transistor 130 is at logic high of 2V, the first N-type transistor 130 is slowly turned on, and the first P-type transistor 110 is gradually turned off. In this transitional time, the first P-type transistor 110 and the first N-type transistor 130 are possible to be turned on at the same time such that a leaking current is generated and power is wasted.